1. Technical Field
The present invention relates in general to data processing systems and in particular to microprocessors. Still more particularly, the present invention relates to an improved method and system for restoring register mapper states for an out-of-order microprocessor.
2. Description of the Related Art
Conventional microprocessors utilize on-chip cache memory to increase memory access rates. Cache memory includes one or more levels of dedicated high-speed memory for storing recently accessed instructions and data. Cache memory technology is based on the premise that microprocessors frequently re-execute the same instructions and/or execute different instructions using recently accessed data. An instruction that depends on one or more preceding instructions to load required data into working operand registers cannot execute until all of the required data has been retrieved from cache or main memory. Furthermore, execution units cannot predict how long it may take to load data into the working operand registers. Older microprocessors handled this uncertainty by delaying execution until the required data is fetched (i.e., by “stalling” the execution pipeline).
Conventional microprocessors utilize speculative instruction execution to address pipeline stalls by enabling a second instruction that is data-dependent on a first instruction to enter an execution pipeline before the first instruction has passed completely through the execution pipeline. In microprocessors that utilize speculative instruction execution, there is a delay between the decision to issue an instruction and the actual execution of the instruction. Thus, in the case of load instructions, there may be a significant delay between the issue of a load instruction and the corresponding data fetch from cache memory. A consumer load instruction, dependent on a delayed instruction, may be issued before confirmation by the cache system that the required load data is available in the cache. When the required load data is not found in the cache, dependent consumer load instructions can execute and access incorrect data.
In order to maintain correctness, microprocessors flush incorrectly executed speculative instructions and their results. Conventional microprocessors detect and correct such misspeculation by tracking instruction dependencies using large physical register mappers, taking “snapshots” of the entire mapper before every instruction dispatch, and rolling back the snapshots to the one taken just before the instruction(s) that caused the exception. The register mappers enable dependency chains to be established based on the snapshots. However these register mapper snapshots are complex and typically consume large amounts of area and power, since many snapshots are usually needed. To enable recovery from cache flushes, microprocessors can also save a previous physical register state for each instruction group and for each physical register type, but this also requires a large amount of memory area and slows the process of register state recovery.